A common characteristic of semiconductor integrated circuit arrays such as a read only memory (ROM) is a pattern of x and y electrical conductors which intersect at cross points at which bit locations are defined. It is also common that the x and y conductors are formed with two different materials (metallic and polysilicon) at two different levels adjacent the semiconductor material and are separated by an insulating layer.
Frequently, the y conductors, hereinafter designated "bit conductors," are alternated with electrically conducting ground lines formed at the same level. Information is stored permanently in such a memory, for example, by forming a switchable short circuit between a selected y conductor and a ground line, switched via an x conductor at a bit location at the intersection of the two conductors. Switching is accomplished, for example, by an N-channel MOS device with a gate accessed via the x conductor.
In this type of arrangement, it is common for each bit conductor to be connected to a drain electrode of, for example, a P-channel MOS device, the source of which is connected to a supply voltage V.sub.DD. The gates of the P-channel devices similarly are connected electrically in parallel to a source of signals .phi.. The ground lines are connected electrically in parallel to the drain of an N-channel MOS device, the source of which is connected to ground. Signals .phi. also are applied to the gate of the (common) N-channel device. Thus, when the P-channel devices are activated, the N-channel device is deactivated and vice versa. Information is stored permanently in such an arrangement by connecting a bit conductor electrically to the next adjacent ground line at a prescribed cross point between the bit conductor and the intersecting x conductor, connection being made through the N-channel device gated via the x conductor as described above.
In the illustrative example described hereinafter, the ROM is word organized and, accordingly, the x conductors are designated "word conductors." In operation of such a ROM with ground lines as described, the signals .phi. are applied to the gates of all the P-channel devices and the (common) N-channel device and electrical currents flow through the bit conductors to the associated ground lines, where short circuits occur at preset bit locations, through the N-channel device to ground. Where a bit conductor and an associated ground line are not shorted together, a voltage difference exists therebetween and a detector connected to the bit conductors indicates this condition.
A ROM is accompanied by a translator or decoder which is operative to select word conductors during operation. In integrated circuit arrangements, the decoder and ROM are formed as part of a single integrated circuit where the decoder is of a form similar to the ROM but turned 90.degree. with respect thereto with metallic "bit conductors" therein electrically connected to polysilicon word conductors of the ROM.
In a microprocessor, the decoder and ROM structures are sometimes also used as a (so-called) programmable logic array (PLA) operative to control various other logic circuits defined in a single semiconductor chip. Electrical conductors connecting the bit conductors of the ROM in prior art arrangements are gathered for external connection, at one end of the bit conductors, into a communication path (bus) which follows along the better part of two sides of the ROM occupying considerable area of the chip. Naturally, chip area is at a premium and any savings in chip area is desirable.